 // Verilog test fixture created from schematic E:\cs3710\Top.sch - Wed Nov 12 15:21:30 2008

`timescale 1ns / 1ps

module Top_Top_sch_tb();

// Inputs
   reg reset;
   reg clock;
	integer i;
//	reg [3:0] switches;

// Output
//	wire [7:0] LED;
// Bidirs

// Instantiate the UUT
   Top UUT (
		.reset(reset),
//		.switches(switches),
//		.LED(LED),
		.clock(clock)
   );
// Initialize Inputs
 
       initial begin
		reset = 1;
		clock = 0;
//		switches = 4'b0;
		
  #100
  
	for(i = 0; i < 10; i = i + 1)
	begin
	#1
	clock = ~clock;
	if(i == 5)
	reset = 0;
	end
end
always
#1 clock = ~clock;
endmodule
